www.neuron.yale.edu

Our lab is developing a hardware-based closed-loop brain machine interface model for evaluating data acquisition systems. NEURON appears to fit in very nicely as one module in this loop.

We are therefore exploring methods for accelerating NEURON's operation so that one or more cortical columns may be modeled in real-time. One proposed solution involves porting the runtime code to Field Programmable Gate Arrays.

I have not found any papers on this topic. Has any work been started in this area?.. or are we chasing a dead project?

Additionally, are any reports available on NEURON's or mNEURON's execution speeds for various sized models. I am mid-way through reading the NEURON book and recognize this question is not completely cut-n-dry. I am simply attempting to validate the scale for a which a network of simply modeled neurons may executed in real-time.

Thanks!

Re: FPGAs, check out the work of Robert Lee at Emory
http://www.bme.gatech.edu/facultystaff/ ... .php?id=35

Re: network benchmarks, see
Migliore, M, Cannia, C., Lytton, W.W., Markram, H. and Hines, M.L. Parallel network simulations with NEURON. Journal of Computational Neuroscience 21:119-129, 2006.
http://www.neuron.yale.edu/neuron/paper ... s_2006.pdf
That said, the performance just keeps getting better all the time as NEURON's algorithms
for distributed simulations of cells and nets are the focus of a major development effort.

Perfect. Thank you for the quick response.

I actually just started reading "Methodology and design flow for assisted neural-model implementations in FPGAs." by R. Lee a few hours ago. Your reference makes me feel better about my current path.