Translating network models to parallel hardware in NEURON

TitleTranslating network models to parallel hardware in NEURON
Publication TypeJournal Article
AuthorsHines, M. L., and Carnevale N. T.
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Preprint available as parallelizing_models_jnm2008.pdf 
Shows how to revise network models so that they will run and produce numerically identical results on either serial or parallel hardware. This allows model development and debugging to be done on readily available local resources, producing code that will run without modification on any single- or multicore PC or Mac, workstation cluster, or parallel supercomputer.